The present invention relates to a byte-switching arithmetic unit, and more particularly to an arithmetic unit for switching operations of data to be subjected to a pre-processing for subsequent parallel processing to image data.
For image processings, data for individual pixels may often comprise integers of 8-bits or 16-bits or fixed decimals. The individual pixel data are used to repeat the same operations for image processings, for which reason the data are subjected to the parallel processings or parallel operations in order to increase an amount of data processings in a unit time. In order to prepare data to be parallel-processed, a pre-processing to the data is carried out by use of the byte-switching arithmetic unit. This byte-switching arithmetic unit is further used to switch or return the parallel-processed results into sequential data.
FIG. 1 is a diagram illustrative of the byte-switching operations, wherein the processing is carried out in 64-bits width by use of three different arithmetic units capable of parallel processings of data in three different bit widths, for example, 8-bits width, 16-bits width and 32-bits width. Inputs comprise two 64-bits numbers "A" and "B", each of which is divided into 8-bits numbers to generate "A1", "A2", "A3", "A4", "A5", "A6", "A7" and "A8" as well as "B1", "B2", "B3", "B4", "B5", "B6", "B7" and "B8" in the high orders.
In the above cases, there are different six operations. The operations in the 32-bits width are to create a first 64-bit order "1H" of "A1", "A2", "A3", "A4", "B1", "B2", "B3" and "B4" as well as to create a second 64-bit order "1L" of "A5", "A6", "A7", "A8", "B5", "B6", "B7" and "B8". The operations in the 16-bits width are to create a third 64-bit order "2H" of "A1", "A2", "B1", "B2", "A3", "A4", "B3" and "B4" as well as to create a fourth 64-bit order "2L" of "A5", "A6", "B5", "B6", "A7", "A8", "B7" and "B8". The operations in the 8-bits width are to create a fifth 64-bit order "3H" of "A1", "B1", "A2", "B2", "A3", "B3", "A4" and "B4" as well as to create a sixth 64-bit order "3L" of "A5", "B5", "A6", "B6", "A7", "B7", "A8" and "B8".
In order to realize the above operations, a set of eight selectors 2 is used for 8-bits, wherein each of the eight selectors 2 has six inputs into which corresponding signals to individual operations are inputted, whereby selecting operations are determined by the kinds of the operations. FIG. 2 is a diagram illustrative of a first conventional circuit comprising a set of eight selectors for 8-bits, wherein each of the eight selectors has six inputs.
FIG. 3A is a circuit diagram illustrative of first type of the selectors having six inputs illustrated in FIG. 2. FIG. 3B is a circuit diagram illustrative of second type of the selectors having six inputs illustrated in FIG. 2.
With reference to FIG. 3A, the six-input selector has five inputs connected to five control signal lines on which control signals are transmitted, wherein if a control signal transmitted on one control signal line is high level "1", then means that this control signal line is selected. The remaining one input of the six-input selector is also connected to a line which is to be selected only when all of the five control signal lines are not selected. The six-input selector comprises a set of six pairs of a transfer gate 10 and an inverter 30. The transfer gate 10 comprises a CMOS circuit which further comprises a pair of n-channel and p-channel MOS field effect transistors 12 and 13. As the scale down of the semiconductor devices to be integrated in a semiconductor integration circuit is advanced, then a reduction in the number of the lines and interconnections might be more effective for reducing the area of the integrated circuit than a reduction in the number of the transistors, for which reason the above selector circuit is designed in order to reduce the number of the lines or interconnections as many as possible. The number of the required transistors is 34 for 1-bit, whilst the 64-bits requires 2176 transistors. The number of the control signal lines extending in the horizontal direction is 5, whilst data signal lines extending in the horizontal direction is 96. Accordingly, a total number of the control signal lines and the data signal lines extending in the horizontal direction is 101.
With reference to FIG. 3B, the six-input selector has six inputs connected to six control signal lines, each of which is selected by the high level signal "1". The selector comprises a set of six pairs of a transfer gate 10 and an invertor 30. The transfer gate 10 comprises a CMOS circuit which further comprises a pair of n-channel and p-channel MOS field effect transistors 12 and 13. The number of the required transistors is 24 for 1-bit, whilst the 64-bits requires 1536 transistors. The number of the control signal lines extending in the horizontal direction is 6, whilst data signal lines extending in the horizontal direction is 96. Accordingly, a total number of the control signal lines and the data signal lines extending in the horizontal direction is 102.
FIG. 4 is a diagram illustrative of a second conventional circuit comprising a set of eight selectors for 8-bits, wherein each of the eight selectors has at most six inputs. The selectors are designed to provide the minimum number of the essential or required inputs for every 8-bits so as to reduce the number of the transistors. Two of a two-input selector 3 are provided for most and least significant 8-bits respectively. Two of a four-input selector 4 are provided for second most and second least significant 8-bits respectively. Two of a six-input selector 5 are provided for third most and third least significant 8-bits respectively. Two of a four-input selector 6 are provided for a center pair of 8-bits respectively. The reduction in the number of the transistors results in drop of the power to be consumed. The power consumption is different among the two-input selector 3, the four-input selector 4, the six-input selector 5 and the four-input selector 6.
The above first conventional eight selector of FIG. 3A designed to reduce the number of the horizontal lines needs 12 control signal lines and a total number 108 of the control signal lines and the data lines and further 992 transistors. The above second conventional eight selector of FIG. 3B designed to reduce the number of the horizontal lines needs 16 control signal lines and a total number 112 of the control signal lines and the data lines and further 512 transistors.
In the above circumstances, it had been required to develop a novel byte-switching arithmetic unit designed to reduce numbers of transistors and lines for reductions in occupied area and a power to be consumed.